RegViz: Visualize GTDLYCR2 Bitfield

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Interpret as GTDLYCR2

DLYBS1=0, DLYEN2=0, DLYEN3=0, DLYBS3=0, DLYEN1=0, DLYBS0=0, DLYBS2=0, DLYEN0=0

PWM Output Delay Control Register 2

DLYBS0	PWM Delay Generation Circuit bypass for channel 0 0 (0): Delay generation circuit of channel 0 bypassed 1 (1): Delay generation circuit of channel 0 not bypassed
DLYBS1	PWM Delay Generation Circuit bypass for channel 1 0 (0): Delay generation circuit of channel 1 bypassed 1 (1): Delay generation circuit of channel 1 not bypassed
DLYBS2	PWM Delay Generation Circuit bypass for channel 2 0 (0): Delay generation circuit of channel 2 bypassed 1 (1): Delay generation circuit of channel 2 not bypassed
DLYBS3	PWM Delay Generation Circuit bypass for channel 3 0 (0): Delay generation circuit of channel 3 bypassed 1 (1): Delay generation circuit of channel 3 not bypassed
DLYEN0	PWM Delay Generation Circuit enable for channel 0 0 (0): Delay generation circuit of channel 0 enabled 1 (1): Delay generation circuit of channel 0 disabled
DLYEN1	PWM Delay Generation Circuit enable for channel 1 0 (0): Delay generation circuit of channel 1 enabled 1 (1): Delay generation circuit of channel 1 disabled
DLYEN2	PWM Delay Generation Circuit enable for channel 2 0 (0): Delay generation circuit of channel 2 enabled 1 (1): Delay generation circuit of channel 2 disabled
DLYEN3	PWM Delay Generation Circuit enable for channel 3 0 (0): Delay generation circuit of channel 3 enabled 1 (1): Delay generation circuit of channel 3 disabled

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